Andrew Nikitin

Verification Engineer with experience in functional verification more than 2 years. Experience of creation test plans and test reports. Experience of work with system of manages different versions. Successful experience of development test benches(System Verilog) and verification blocks of image processing and large system of such blocks. Successful experience of verification blocks in normal and abnormal situations with constrained random, coverage.

Job functions and experience: • Experience of design of test plans and test reports • Experience of design of test benches in System Verilog • Experience to create reference models of image processing in SystemC и System Verilog • Experience of verification blocks of image processing and system of such blocks (for example blocks of stabilization, resample, imposition, different filters, frame buffers, controllers SRAM, flash-memory, DDR). • Knowledge methodology UVM, OVM, VMM