Dr. Davide Lequile

Freelancer-Contractor since 2009. Expert in the area of ASIC RTL conception and development, with particular attention to Speed and Power optimization. Used to work closely with management, often involved in customer meetings. My main domains of expertise are : ASIC / SoC / IPs Digital Front-End Designer Engineer involved in : -RTL Micro-architecture Conception/Development -VHDL / (System)Verilog coding -Validation/Verification

RTL Designer Engineer Specialist

Scalable and energy efficient Radio-Access-Network (RAN) parallel compute networks for 5G/IoT. In charge for the RTL development of innovative new features to improve multi-channels communication between multiple CPUs / DSPs / Accelerators.

SoundWire-I3S (SWI3S) Peripheral IP: In charge for the RTL development of all the modules and IP of the new MIPI Audio interface Peripheral unit used for transporting audio streams and control information together on a single link, in half-duplex fashion, single-ended PHY: Link-Controller, Command-Transport-Decoder, Payload-Controller for Audio Chip

Time-of-Flight 3D Camera project: In charge for the RTL development of new: DVGA-Sensor-Matrix Readout Controller, controllers for ADC, Sensor, DAC and Exposure. Motion Detection unit, compensation of ADCs results, new memory controller access mode, mod of Frequency ramper generator. Linting and debug and supporting the verification & firmware teams to correctly build their testcases and FW codes through the analysis of their failing tests. Documentation update.

Supporting the ASIC RTL team for the IoT audio system development of a smart wearables technology, SystemVerilog/VHDL. Involved in all the different ASIC flow steps. SoC with ARM Cortex-M3 core.

Supporting the ASIC RTL team for the 5G system development. In charge for the BB & Radio Controller Subchips & Subsystems Integration (CCCR, EVC, GPIO_CTRL, SPI, LED, Synopsys I3C Master & Slave DW IPs, PA_CTRL, SYNC, AXI_CTRL_UART, DB_UART, NIC400). RTL development and modification of internal IPs and Filters Dynamic Power Save optimization. Writing Design Specification documentation. Supporting verification & validation. Mainly using SystemVerilog as RTL description language.

Supporting the ASIC team going to the tape-out for a mixed-signal Fingerprint ASIC SoC with ARM Cortex-M3 core.

Writing design specifications, RTL conception and Verilog development of: asynchronous interfaces for fast data exchange – data path blocks – RTL modifications for Power optimization - blocks integration – block level testbench – simulation – synthesis scripts

Supporting the RTL design team for the development of a mixed-signal fingerprint SoC ASIC. Main tasks: clock/reset/power management unit, dft controller, modules modelling, digital thermometer, srams integrations, design spec writing.

-Supporting the Video Coder RTL team for the ASIC design development flow -also Supervisor of main activities and designers.

RTL development and VHDL coding of a JPEG Encoder with Pipelined Parallel Architecture.

Consultant in NXP-Philips to support the RTL design team developing sub-blocks for a Bluetooth digital receiver ARM based SoC. Activities: Old architecture improvement - data bus control interface, Clocks & Power management unit RTL conception and VHDL development - Top level integration - test bench development - simulation - Top porting and Quartus synthesis on Altera FPGA -drawing up user manual and release document

Front-End Digital Designer - RTL Conception, VHDL (Verilog) coding, Validation, Synthesis at sub-block and top level. Main activities: -New DSP (Risc-VLIW) RTL Micro-Architecture development -ASIC / SoC development and implementation -ARM (Micro & peripherals) design implementation -Multimedia Platform for NOKIA Mobile (NOMADIC): Core Subsystem RTL development and implementation.

Master, Electronic Engineering, Specialization in Microelectronics, Vote: 110/110 Cum Laude (with Honors)