Dr. Davide Lequile
Freiberuflich, Principal RTL Designer, Freelance Company
London, Vereinigtes Königreich
Werdegang
Berufserfahrung von Davide Lequile
Bis heute 15 Jahre und 6 Monate, seit Jan. 2009
Experienced ASIC RTL Designer / Freelance
Confidential
Freelancer-Contractor since 2009. Expert in the area of ASIC RTL conception and development, with particular attention to Speed and Power optimization. Used to work closely with management, often involved in customer meetings. My main domains of expertise are : ASIC / SoC / IPs Digital Front-End Designer Engineer involved in : -RTL Micro-architecture Conception/Development -VHDL / (System)Verilog coding -Validation/Verification
Bis heute 15 Jahre und 6 Monate, seit Jan. 2009
Principal RTL Designer
Freelance Company
RTL Designer Engineer Specialist
SoundWire-I3S (SWI3S) Peripheral IP: In charge for the RTL development of all the modules and IP of the new MIPI Audio interface Peripheral unit used for transporting audio streams and control information together on a single link, in half-duplex fashion, single-ended PHY: Link-Controller, Command-Transport-Decoder, Payload-Controller for Audio Chip
Time-of-Flight 3D Camera project: In charge for the RTL development of new: DVGA-Sensor-Matrix Readout Controller, controllers for ADC, Sensor, DAC and Exposure. Motion Detection unit, compensation of ADCs results, new memory controller access mode, mod of Frequency ramper generator. Linting and debug and supporting the verification & firmware teams to correctly build their testcases and FW codes through the analysis of their failing tests. Documentation update.
6 Monate, Mai 2020 - Okt. 2020
Principal ASIC RTL Designer - Freelance
Qualcomm
Supporting the ASIC RTL team for the IoT audio system development of a smart wearables technology, SystemVerilog/VHDL. Involved in all the different ASIC flow steps. SoC with ARM Cortex-M3 core.
Supporting the ASIC RTL team for the 5G system development. In charge for the BB & Radio Controller Subchips & Subsystems Integration (CCCR, EVC, GPIO_CTRL, SPI, LED, Synopsys I3C Master & Slave DW IPs, PA_CTRL, SYNC, AXI_CTRL_UART, DB_UART, NIC400). RTL development and modification of internal IPs and Filters Dynamic Power Save optimization. Writing Design Specification documentation. Supporting verification & validation. Mainly using SystemVerilog as RTL description language.
3 Monate, Juni 2017 - Aug. 2017
Principal ASIC RTL Designer / Freelance
Ensilica
Supporting the ASIC team going to the tape-out for a mixed-signal Fingerprint ASIC SoC with ARM Cortex-M3 core.
3 Monate, Mai 2016 - Juli 2016
Principal ASIC RTL Designer / Freelance
Confidential
Writing design specifications, RTL conception and Verilog development of: asynchronous interfaces for fast data exchange – data path blocks – RTL modifications for Power optimization - blocks integration – block level testbench – simulation – synthesis scripts
4 Monate, Sep. 2015 - Dez. 2015
Principal ASIC RTL Designer / Freelance
S3 Group
Supporting the RTL design team for the development of a mixed-signal fingerprint SoC ASIC. Main tasks: clock/reset/power management unit, dft controller, modules modelling, digital thermometer, srams integrations, design spec writing.
8 Monate, Juli 2014 - Feb. 2015
Principal ASIC RTL Designer / Freelance
Imagination Technologies
-Supporting the Video Coder RTL team for the ASIC design development flow -also Supervisor of main activities and designers.
4 Monate, Jan. 2013 - Apr. 2013
Principal ASIC RTL Designer / Freelance
Confidential
RTL development and VHDL coding of a JPEG Encoder with Pipelined Parallel Architecture.
1 Jahr und 3 Monate, Feb. 2007 - Apr. 2008
Sr ASIC/Fpga Designer
Astek / NXP-Philips
Consultant in NXP-Philips to support the RTL design team developing sub-blocks for a Bluetooth digital receiver ARM based SoC. Activities: Old architecture improvement - data bus control interface, Clocks & Power management unit RTL conception and VHDL development - Top level integration - test bench development - simulation - Top porting and Quartus synthesis on Altera FPGA -drawing up user manual and release document
5 Jahre und 10 Monate, Mai 2000 - Feb. 2006
Sr Digital Designer Engineer
STMicroelectronics
Front-End Digital Designer - RTL Conception, VHDL (Verilog) coding, Validation, Synthesis at sub-block and top level. Main activities: -New DSP (Risc-VLIW) RTL Micro-Architecture development -ASIC / SoC development and implementation -ARM (Micro & peripherals) design implementation -Multimedia Platform for NOKIA Mobile (NOMADIC): Core Subsystem RTL development and implementation.
Ausbildung von Davide Lequile
- Bis heute
Microelectronics
Università degli Studi di Napoli Federico II
Master, Electronic Engineering, Specialization in Microelectronics, Vote: 110/110 Cum Laude (with Honors)
Sprachen
Italienisch
Muttersprache
Englisch
Fließend
Französisch
Fließend