Javed Alam

Angestellt, design and verification, JAVED ALAM
Hyderabad, India

Skills

Verilog VHDL
system verilog
UVM
Python
NAND

Timeline

Professional experience for Javed Alam

  • Current 3 years and 8 months, since Jan 2023

    design and verification

    JAVED ALAM

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