Joel Viray

• Develop and implement robust electrostatic discharge (ESD) and electrical overstress (EOS) protection design rules, guidelines and methodologies, and include mitigation of latch-up effects. • Work closely with several internal groups such as various users in different fabs, design enablement group, device owners, spice model development teams, etc., to ensure proper implementation of ESD to meet corporate and customer needs and goals.

• Work for pad ring and power management for Altera devices and its proliferations and work closely with ICD and Package team to ensure the quality delivery is meeting design intent

• Responsible on Custom IC layout in Bipolar, CMOS and BiCMOS technologies from circuit schematics using Cadence Virtuoso layout toolset and JEDAT EDA tools.