Ali Kokhazadeh

- Design and optimization of FPGA-based convolutional neural network accelerators - Design and hardware implementation of a processor targeting big-data clustering

Designed and implemented digital systems using VHDL/Verilog for various projects, including: • RTL design of a pipelined ARM968E-S processor with cache. • RTL design of an approximate multiplier. • RTL design of an approximate Natural Logarithm unit. Delivered lectures on computer engineering topics, including Digital Logic Design and Computer Architecture.

I was in charge of teaching various computer engineering courses, namely: Digital Logic Design, Computer Architecture, Programming, Multimedia Systems, Data Structure and Algorithm, etc.

besides my research on video coding, I did hardware design, implementation and optimization of various H.264/AVC encoder modules during the project "Design and Hardware Implementation of an H.264/AVC Video Codec." These modules include: Inter Motion Compensation & Skip, Inter Mode Decision, Search Windows Memory, and DDR Interface.

I graduated from the University of Tehran, one of the top-most universities of Iran. Master's Thesis: Improving Design Space Exploration of MP-SoC Systems Using Design Space Pruning

I graduated from the University of Tehran, one of the top-most universities of Iran. Bachelor's Project: Design and Implementation of a Pipeline Processor with a Direct-mapped Cache using Verilog HDL.