B. GANGADHAR GOWD

 Applied fundamental analog layout flow and matching techniques during layout development.  Utilized knowledge of TSMC 7nm process layers while executing layout tasks.  Identified and addressed crosstalk, latch-up, EM, and antenna violations to ensure design reliability.  Implemented Op-Amp layout in TSMC 7nm and achieved base DRC clean compliance.

 Designed & validated standard cell libraries (basic, clock, sequential, & complex cells) for Intel 14A & 18A technology nodes.  Performed standard cell architecture rule validation and created structured test cases to stabilize PDK environments.  Executed block-level metal ECOs post base tape-out with clean DRC/LVS closure.  Implemented top-metal routing and power mesh distribution at the SoC level in management with PDN teams.