Skip navigation

Debajit Paul

Angestellt, FPGA Validation engineer, altera
Bangalore, India

Skills

static timing analysis
Quartus tool
Field Programmable Gate Array (FPGA)
Timing Analysis
Simulation

Timeline

Professional experience for Debajit Paul

  • Current 1 year and 9 months, since Jan 2025

    FPGA Validation engineer

    altera

XING members with similar profiles

Suprabha Ghosh

Student Researcher

Ilmenau

Zhaxylyk Abzalov

Lead Electrical Engineer

Vienna

Thomas Möhring

SSE Timing Methodology and Signoff

München

Lars Altmann

Konzeptingenieur

München

Obulreddigari Gayathri

---

Bengaluru

Ralf Woehler

Manager, Research & Development FPGA

Richardson

Roger Sharp

Vice President

Jacksonville

Kalpitha Ramachandra

FPGA Developer

Augsburg

IGOR MULLIN

PLC Developer/SPS Programmer | Engineer Automation

Uljanowsk

Shadaab Mohammed

Master Thesis

Deggendorf

Mohammad Salman Farshi

Control, Microsystems, Microelectronics

München

Arvind Anche

Instrumentation and Electronics

Munich

Vijay Ananth

---

Chemnitz

Anish Joboy Augustine

SoC Design Engineer

Bangalore

Khosro Jourabchi

Senior Design Engineer (ASIC/FPGA Design / Virtual prototyping)

Hannover

Ajaykrishna Ettiyil

---

Regensburg

Sunetra Pal

---

Munich

Kadir Tastepe

Machine Learning Engineer / Working Student

Heidelberg

Sergey Dubinin

Staff Digital Design and Verification Engineer | CSS dpt.

Austria

Mohamed Elmekawy

ASIC physical design engineer

Dresden

XING – The jobs network

  • Over 1 million jobs

    Find just the right job for you on XING.

  • Job offers just for you

    Get found by employers and over 20,000 recruiters.

  • 21 million members

    Connect with new people and gather inspiration to boost your working life.

  • Free membership

    Basic membership is free, but the opportunities are priceless.

Browse over 21 million XING members

Last name:

ABCDEFGHIJKLMNOP
QRSTUVWXYZ