André Souto

Implementation of DSP algorithms on FPGAs for a phase array based medium range radar. Took the initiative to develop improvements such as: - A GNU Makefile based flow for Xilinx PlanAhead - Python tools for DSP data analysis and for low-level FPGA register access

• Analysis of telecommunication protocols and their test procedures • Development of test plans, test cases and respective effort estimation • Development of testing tools in Ruby and Python • Development and execution of manual and automated tests Highlights: • Increased VLAN test capacity from 1 to 800 tests per minute • Reduced the time taken for an Ethernet protocol test with over 20 L2/L3 protocols from 3 days to 4 minutes

• Managed 2 product development projects with a team of 10 engineers and area coordinators from R\&D and industrial areas, being responsible for schedules and task backlog control. • Responsible for contact with partners and suppliers from USA, China and Israel and for answering RFPs from customers such as Telefónica and Copel. Highlights: • Led the development of the first GPON product of the company • Led the first OEM project of the company • Coordinated ANATEL certification of 2 GPON modems

• Development of programmable logic in VHDL for FGPAs and CPLDs • Simulation using ModelSim • Debugging using ChipScope • Development of testing and API scripts in Lua. Highlights: • Experience with interfacing with DDR2/3 external memories, Ethernet PHYs (MII, GMII, RGMII), local bus, SerDes, among others. • Developed the memory management unit (MMU) of a TDM/Ethernet processor